\doxysection{DMA\+\_\+\+Stream\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_d_m_a___stream___type_def}{}\label{struct_d_m_a___stream___type_def}\index{DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}}


DMA Controller.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___stream___type_def_af893adc5e821b15d813237b2bfe4378b}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___stream___type_def_a2cc2a52628182f9e79ab1e49bb78a1eb}{NDTR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___stream___type_def_adbeac1d47cb85ab52dac71d520273947}{PAR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___stream___type_def_a965da718db7d0303bff185d367d96fd6}{M0\+AR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___stream___type_def_a142ca5a1145ba9cf4cfa557655af1c13}{M1\+AR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_d_m_a___stream___type_def_aad3d78ab35e7af48951be5be53392f9f}{FCR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
DMA Controller. 

\label{doc-variable-members}
\Hypertarget{struct_d_m_a___stream___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_d_m_a___stream___type_def_af893adc5e821b15d813237b2bfe4378b}\index{DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}!CR@{CR}}
\index{CR@{CR}!DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_d_m_a___stream___type_def_af893adc5e821b15d813237b2bfe4378b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Stream\+\_\+\+Type\+Def\+::\+CR}

DMA stream x configuration register \Hypertarget{struct_d_m_a___stream___type_def_aad3d78ab35e7af48951be5be53392f9f}\index{DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}!FCR@{FCR}}
\index{FCR@{FCR}!DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}}
\doxysubsubsection{\texorpdfstring{FCR}{FCR}}
{\footnotesize\ttfamily \label{struct_d_m_a___stream___type_def_aad3d78ab35e7af48951be5be53392f9f} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Stream\+\_\+\+Type\+Def\+::\+FCR}

DMA stream x FIFO control register \Hypertarget{struct_d_m_a___stream___type_def_a965da718db7d0303bff185d367d96fd6}\index{DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}!M0AR@{M0AR}}
\index{M0AR@{M0AR}!DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}}
\doxysubsubsection{\texorpdfstring{M0AR}{M0AR}}
{\footnotesize\ttfamily \label{struct_d_m_a___stream___type_def_a965da718db7d0303bff185d367d96fd6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Stream\+\_\+\+Type\+Def\+::\+M0\+AR}

DMA stream x memory 0 address register \Hypertarget{struct_d_m_a___stream___type_def_a142ca5a1145ba9cf4cfa557655af1c13}\index{DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}!M1AR@{M1AR}}
\index{M1AR@{M1AR}!DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}}
\doxysubsubsection{\texorpdfstring{M1AR}{M1AR}}
{\footnotesize\ttfamily \label{struct_d_m_a___stream___type_def_a142ca5a1145ba9cf4cfa557655af1c13} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Stream\+\_\+\+Type\+Def\+::\+M1\+AR}

DMA stream x memory 1 address register \Hypertarget{struct_d_m_a___stream___type_def_a2cc2a52628182f9e79ab1e49bb78a1eb}\index{DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}!NDTR@{NDTR}}
\index{NDTR@{NDTR}!DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}}
\doxysubsubsection{\texorpdfstring{NDTR}{NDTR}}
{\footnotesize\ttfamily \label{struct_d_m_a___stream___type_def_a2cc2a52628182f9e79ab1e49bb78a1eb} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Stream\+\_\+\+Type\+Def\+::\+NDTR}

DMA stream x number of data register \Hypertarget{struct_d_m_a___stream___type_def_adbeac1d47cb85ab52dac71d520273947}\index{DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}!PAR@{PAR}}
\index{PAR@{PAR}!DMA\_Stream\_TypeDef@{DMA\_Stream\_TypeDef}}
\doxysubsubsection{\texorpdfstring{PAR}{PAR}}
{\footnotesize\ttfamily \label{struct_d_m_a___stream___type_def_adbeac1d47cb85ab52dac71d520273947} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t DMA\+\_\+\+Stream\+\_\+\+Type\+Def\+::\+PAR}

DMA stream x peripheral address register 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
